1. Field of the Invention
The invention generally relates to processors and, in particular, to processors employing power-saving modes.
2. Description of the Related Art
Typical microcontrollers include processors that have power-saving modes (e.g., idle and powerdown modes). These modes are power reduction modes for use in applications where power consumption is a concern. User-programmed software instructions activate these modes by writing to a power saving register. The program execution halts, but resumes when the power saving mode is exited by an external interrupt or hardware reset.
FIG. 1 illustrates a power saving mode for a sequential processor 1 that is implemented in an Intel microcontroller (MCS 51). In this Intel Architecture the core processor utilizes machine cycles, each cycle including six states (i.e., S1-S6). Each state includes a first phase and a second phase. The phase one clock (PH1) and the phase two clock (PH2) provides two non-overlapping clocks for use by the computer system. Using non-overlapping clocks in a microprocessor architecture is well known in the art.
FIG. 1 also illustrates software code that includes a plurality of instructions. In the MCS a power saving instruction (e.g., powerdown instruction) is executed in state four (S4) of the machine cycle. Once the powerdown instruction has been executed, the phase clocks (PH1 and PH2) are frozen in the state in which they were when the power saving instruction was executed.
Since the phase clocks are both frozen, the program execution halts. An external source (i.e., a hardware reset or a external interrupt) must be utilized to bring the processor out of the power saving mode.
Taking the case of an external interrupt, once an external interrupt is detected, the phase clocks are restarted first, completing its current machine cycle, before branching to an interrupt service routing (ISR). The first instruction in the ISR is the first instruction executed by the processor when it comes out of the power saving mode. Please note that the first instruction is the first instruction being executed since the power saving instruction.
After the instructions in the ISR are executed, the last instruction in the ISR is a return from interrupt instruction. The return passes control back to the software code that was running before the power saving mode and branch to the ISR. Program execution of the software code resumes at the next instruction (i.e., the instruction immediately following the power saving instruction).
This Intel Architecture for the MCS has the following attributes. First, the phase clocks are stopped (i.e., frozen) within the power saving instruction cycle. Second, if wake-up from a power saving mode is accomplished by an interrupt, the next instruction executed is guaranteed to be the first instruction in the corresponding ISR. Third, upon return from the ISR, the instruction, immediately following the power saving instruction, is guaranteed to be executed next. Thus, this architecture provides both predictability and ensures uniformity in both the wake-up from a power saving mode and also the return from an ISR.
FIG. 2 illustrates a pipe-lined processor 3 in which instructions are segmented into stages for processing, and the stages of different instructions are overlapped (i.e., stages of different instructions are processed concurrently). For example, a first instruction (e.g., power saving instruction) includes three stages: a Fetch stage, a Decode and Read stage, and an Execute and Write-Back stage. In the first state (S1), the processor fetches the first instruction In state two (S2), the processor decodes the first instruction while fetching the second instruction. In S3, the processor concurrently executes the first instruction, decodes the second instruction and fetches the third instruction.
As can be seen from FIG. 2, the phase clocks are not frozen until the processor processes the Execute and Write-back stage of the third instruction (i.e., clocks are frozen in some state after S3). The phase clocks are frozen in some state after S3 because there is a delay in setting the bit set in power saving register.
Although this pipe-lined processor improves performance of the processor, the pipe-lined nature of the processor introduces uncertainty as to 1) when the clocks are frozen, 2) which instruction is executed upon wake-up from power saving modes and also 3) which instruction is executed upon a return from the interrupt service request (i.e., MCS51 attributes are no longer guaranteed).
For example, if the second instruction is an instruction that executes and completes in one stage, the second instruction will be executed before the phase clocks are frozen. In this case, upon wake up by an external interrupt, the first instruction in the ISR 37 occurs after the second instruction or later. Moreover, when the ISR 37 returns to the software code, a third instruction is the next instruction executed.
As can be seen from FIG. 2, in a pipelined processor the last instruction in the software code, before going into a power saving mode and branching to the ISR and the instruction after which it returns, depends upon the complexity of the second instruction (i.e., the number of stages required by the second instruction to complete). Thus, the branch to the ISR may occur after the power saving instruction, after a second instruction, or even a third instruction (as shown) depending on what the second and third instructions are.
In the example illustrated in FIG. 2, the power save bit is set in State 5 (S5). In State 6 (S6) the second instruction is executed. In State 7 (S7), the execution and write, associated with the third instruction, is carried out. Upon wake-up in State 8 (S8), the execution and write, associated with the third instruction, is completed. Thus, in this example, the branch to the ISR occurs during the third instruction, and the return from ISR occurs before the fourth instruction. This is very undesirable because the computer system behaves unpredictably, since this behavior is code specific (i.e., it can change for different software programs and even within different sections of the same program).
Accordingly, there is a need for a method and apparatus to provide predictability and uniformity in 1) when the program execution halts, 2) which instruction is executed upon wake-up and 3) which instruction is executed after a return from the ISR in a pipelined processor.
One proposed solution is to provide additional circuitry in the processor to detect a power saving command (i.e., idle and powerdown). The additional circuitry in the processor detects and decodes these power saving commands and correspondingly flushes any following commands before the branch to the ISR.
One disadvantage of this approach is that additional circuitry is required to treat the power saving command as a special hardware event. Additional circuitry is necessary to decode this special instruction and all the addressing modes for the operands of this special command.
These addressing modes includes register addressing (where the instruction specifies the register which contains the operands), immediate addressing (where the instruction contains the operand), direct addressing (where the instruction contains the operand address), indirect addressing (where the instruction specifies the register containing operand addresses), displacement addressing (where the sum of register and the assigned offset specified by the instruction is the operand address), relative addressing (where the instruction contains a relative offset from the next instruction to target the address) and the bit addressing (where the instruction contains the bit address). Accordingly, additional circuitry is required to decode each of the above-noted cases.
In addition, circuitry is further required for flushing the following commands that are in the pipeline at the time of entering a power saving mode. This process of flushing commands is complex and requires its own overhead.
Consequently, there is a need for a method and apparatus for providing power saving modes to a pipeline microprocessor that ensures uniformity and predictability upon wake-up and return from ISR without the problems noted in the proposed solution.